A tri-state multiplexer (MUX) (FIG. 1) is often used in designs to save chip area and reduce delay. But if a tri-state MUX is incorrectly used, undesirable situations like erroneous/unpredictable functional behavior, excessive power consumption, and/or irreparable physical damage to the chip may arise. To avoid these problems, the designer must either verify that such conditions cannot happen or add a special circuitry to guarantee that such conditions never happen. A priority encoder is often used as the special circuitry. For verification, simulation has been used in the past.
A tri-state multiplexer can fail in at least two ways. If no select line is asserted, then the multiplexer output is not driven (i.e. a tri-state condition occurs). This can cause gates driven by the multiplexer to draw excessive current and to have uncertain output values. If more than one select line is asserted at the same time there can be a direct current path between their respective data lines. Data contention and high/excessive currents can results. Multiplexers in which neither of these conditions is present are called passing MUXs and others are called failing MUXs.
Though a priority encoder guarantees the passing condition, it increases the delay of the design, consumes chip area and increases power consumption. Even when the logic without the priority encoder already satisfies the passing condition, a priority encoder is often used just to be safe, because there has not been an efficient and effective way to verify the fact that the priority encoder is not necessary.
Simulation has been used to check the correctness of designs with tri-state MUXes. Due to the prohibitive cost, not all vectors are simulated. If there exists a vector which creates an undesirable condition at a tri-state MUX, simulation cannot detect it unless the vector is simulated. The designer is responsible to come up with a set of vectors to be simulated to check if there is a design error in using tri-state MUXes. If the designer failed to include the right vector in his or her vector set, a design error may not be detected and, thus production of malfunctioning chips may happen. The error may require a costly re-design cycle, or in the worst case, the malfunctioning chips may be shipped to the customers. Since not all vectors are simulated, it is impossible to guarantee the correctness of a design in terms of the tri-state MUX operation with the conventional simulation approach. This lack of guarantee has been the main reason why priority encoders were used despite the disadvantages in area and delay, to avoid more costly potential setbacks.
For test generation, Automatic Test Pattern Generation (ATPG) is devised to avoid generating a test vector that creates the failing condition at a tri-state MUX. The passing condition at a tri-state MUX is often referred as a design constraint which ATPG should meet with the generated test vectors. When ATPG finds that a test vector which meets the design constraints does not exist, it reports the fact. Hence ATPG may find a design error in some cases. However, if there is a vector meeting the passing condition, ATPG just chooses the vector and does not care if there is a vector with the failing condition. In other words, a circuit where ATPG generates test vectors without design constraints violation, is not necessarily a correct design. For designs using scan test methodology, some additional logic is required to avoid the failing condition at tri-state MUXes during scan shifting, even though the test vectors themselves do not create the failing condition. A priority encoder is an example of such additional logic, which as discussed above, is undesirable .